1 standard products UT54ACS163/ut54acts163 4-bit synchronous counters datasheet november 2010 www.aeroflex.com/logic features ? internal look-ahead for fast counting ? carry output for n-bit cascading ? synchronous counting ? synchronously programmable ? 1.2 cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack ? UT54ACS163 - smd 5962-96554 ? ut54acts163 - smd 5962-96555 description the UT54ACS163 and the ut54acts163 are synchronous presettable 4-bit binary counters that feature internal carry look- ahead logic for high-speed counting designs. synchronous op- eration occurs by having all flip-flops clocked simultaneously so that the outputs ch ange coincident with each other when in- structed by the count-enable inputs and internal gating. a buff- ered clock input triggers the four flip-flops on the rising (posi- tive-going) edge of the clock input waveform. the counters are fully programmab le (i.e., they may be preset to any number between 0 and 15). presetting is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with th e load data after the next clock pulse. the clear function is synchronous and a low level at the clear input sets all four of the flip-flo p outputs low after the next clock pulse. this synchronous clear allows the count length to be mod- ified by decoding the q outputs for the maximum count desired. the counters feature a fully independent clock circuit. changes at control inputs (enp, ent, or load ) that modify the operat- ing mode have no effect on the contents of the counter until clocking occurs. the function of the counter (whether enabled, disabled, loading, or counting) w ill be dictated solely by the conditions meeting the stable setup and hold times. the devices are characterized over full military temperature range of -55 c to +125 c. pinouts 16-pin dip top view 16-lead flatpack top view logic symbol 1 2 3 4 5 7 6 16 15 14 13 12 10 11 clr clk a b c d enp v dd rco q a q b q c q d ent 8 9 v ss load 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 89 clr clk a b c d enp rco q a q b q c q d ent v ss load (1) clr (9) load m1 5ct=0 ctrdiv 16 (10) ent g3 (7) enp g4 (2) clk (3) a (4) b (5) c (6) d (15) rco (14) q a (11) q d m2 c5/2,3,4+ (12) q c (13) q b 1,5d (1) (2) (4) (8) 3ct = 15 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publi- cation 617-12.
2 function table h = high voltage level h = high voltage level one setup time prior to the lo w-to-high clock transition l = low voltage level l = low voltage level one setup time prio r to the low-to-hig h clock transition notes: 1. the rco output is high when ent is high and the counter is at terminal count hhhh. 2. the high-to-low trans ition of enp or ent should only occur while clk is high for conventional operations. 3. the low-to-hi gh transition of load or clr should only occur wh ile clk is high for co nventional operations. logic diagram operating mode clr clk enp ent load data a,b,c,d q n rco reset (clear) l x x x x l l parallel load h 3 h 3 x x x x l l l h l h l 1 count h 3 h h h x count 1 inhibit h 3 h 3 x x l 2 x x l 2 h 3 h 3 x x q n q n 1 l (2) (1) (9) (7) (10) (3) (4) (5) (6) (14) (12) (13) (11) (15) q a q b q c q d rco data d data c data b data a ent enp load clr clk c d q q c d q q c d q q c d q q
3 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional oper ation of the device at these or any other co nditions beyond limits indicated in the operational sections is no t recommended. exposure to abs olute maximum rating conditions for extended period s may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage 0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
6 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h1 ) of 0ns can be assumed if data setup time (t su1 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk to q n 4 24 ns t plh clk to q n 4 22 ns t phl clk to rco 4 22 ns t plh clk to rco 4 24 ns t phl ent to rco 1 13 ns t plh ent to rco 1 14 ns f max maximum clock frequency 77 mhz t su1 a, b, c, d setup time before clk 6 ns t su2 load , enp, ent, clr low or high setup time before clk 6 ns t h1 3 data hold time after clk 1 ns t h2 all synchronous inputs hold time after clk 1 ns t w minimum pulse width clr low clk high clk low 7 ns
7 packaging side-brazed packages
8 flatpack packages
9 UT54ACS163/ut54acts163: smd 5962 ***** ** * * * * lead finish: (notes 1 & 2) a = solder c = gold x = optional package type: x = 16-lead ceramic botto m-brazed dual-in-line flatpack c = 16-lead ceramic side-brazed dip class designator: q = qml class q v = qml class v device type: 01 drawing number : 96554 = UT54ACS163 96555 = ut54acts163 total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, pa rt marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2 . device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-883 test method 1019 condition a.
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